Memories in digital computers usually include a plurality of banks of dynamic random access memory (DRAM) chips. For example, a 80386DX system controller can support four banks of DRAMs, each comprising three (3) DRAM sizes. In addition, the foregoing system controller can support twenty-five (25) different memory map options, and many of the memory map options involve mixed DRAM sizes. Furthermore, the foregoing controller can also support both word and block interleaving techniques for pairs of like size banks of DRAMs. In addition, the concept of page mode can be introduced into the foregoing system. Using page mode techniques, at the end of a memory cycle, the address bits which access the row and the bankselect are latched. During the next memory access, the latched address bits are compared to the new address bits and if the addresses match, a "page hit " occurs and the memory cycle is shortened. The concept of combining interleaving and page mode techniques has been attempted, however, variable DRAM sizes were not involved. For example, U. S. Pat. No. 4,924,375 discloses the concept of combining page mode and interleaving techniques, but the DRAM sizes are the same in each pair of banks. This utilization of DRAMs of the same size in each pair of banks presents a limitation in the foregoing system.
In view of the foregoing, it has become desirable to develop apparatus for facilitating page mode operations in a wide variety of memory map options, including variable size DRAMs, and different interleaving options.